Palavra-chave: LOW TEMPERATURE

STACKED NANOWIRES FABRICATION PROCESS SUBSTRATE EFFECT JUNCTIONLESS NANOWIRE TRANSISTORS FLOATING BODY SILICON INTERLAYER BURIED OXIDE INTERFACE MULTIPLE GATE NANOTECNOLOGIA NANOWIRE MOSFET STRAIN CRYOGENICS JUNCTIONLESS NANOELECTRONICS METAL GATE DEVICE PROCESSING HIGH FREQUENCY PHOTOSYNTHESIS ANALOG APPLICATIONS COLD PROTECTION BUFFER SENSOR DE TEMPERATURA SACCHARUM SP TRAP DENSITY BACKGROUND PRESSURE GC SOI MOSFET CURRENT MIRROR CRYOELECTRONICS MICROELECTRONICS SELF-HEATING EFFECT SUBMICROM WATER DEFICIT MEASUREMENTS DIBL TECNOLOGIA SOI PHOTODIODE NANOWIRE-BASED TRANSISTORS SUGARCANE WHEAT MODELO ANALÍTICO PROCESS TECHNOLOGY PIN DIODE SERIES ASSOCIATION PARAMETER EXTRACTION ANALYTICAL MODEL BUNCH COVER DLC FILM SIMULATION TUNABLE RESISTOR NEW DEVICES NOISE SOLAR CELL DEEP-SUBMICROMETER MUSA SPP. HARMONIC DISTORTION TRIPLE GATE TEMPERATURE MOBILITY DEGRADATION SUBSTRATE INTERFACE SOI MOSFET RADIATION ASCORBIC ACID CARBOHYDRATES ELECTRICAL CHARACTERIZATION HIGH-K DIELECTRICS PEEL BROWNING THREE-DIMENSIONAL NUMERICAL SIMULATION HIGH TEMPERATURE SUBSTRATE FINFET MODELING EXTRACTION METHOD DOUBLE GATE TRANSISTORS THRESHOLD VOLTAGE