Palavra-chave: CRYOGENICS

LOW TEMPERATURES ELECTRICAL CHARACTERIZATION STACKED NANOWIRES MULTIPLE-GATE TRANSISTORS TEMPERATURE NANOWIRE-BASED TRANSISTORS GATE INDUCED DRAIN LEAKAGE COMPACT MODELING CRYOELECTRONICS SOI MOSFET LOW TEMPERATURE NANOWIRE MOSFET SELF-HEATING EFFECT CMOS TECHNOLOGY PARAMETER EXTRACTION JUNCTIONLESS NANOWIRE TRANSISTORS SUBSTRATE BIAS NANOWIRE CMOS TCAD TRIDIMENSIONAL SIMULATION NANOSHEET MOSFET